1. Mixed Signal Circuits for Super IC
The electrical erasable and programmable EEPROM memory has received wide attention in the last decade. Both the technological advances and broad product applications has made it the most emerging candidate for implementing SOC level memory component integrations.
On the process and device technology front, the general practice has been focused on the miniaturization of the physical size of the storage bit, scaling down the cell operating voltages and currents and therefore lowering power consumptions, implementing multilevel signal storages per physical cell area, and building up on chip apparatus to manage per bit, byte, large and partial arrays, resource sharing schemes. The ultimate goals are to achieve the highest level of system integration with mixed analog, memory and logic circuits (AMLC) in a common chip; and therefore to improve IC devices with performance, reliability, system efficiency and capacity.
2. The Densest Cells of any Memory and Logic Arrays in Si
A Flash memory cell, with its multiple bit (2) storage capability in one physical cell layout, is a good choice to implement information storage devices. The density, power, and speed capability of Flash arrays exceed that of rotating disks, so the semiconductor EEPROM is replacing the mechanical disk medium in many applications. The Flash memory cell may also replace DRAM/SRAM if the speed performance is improved besides its superior property of being nonvolatile and having a density of multi-level per cell for information storage. However, little work was developed to employ the FLASH technology to logic applications. Some work was reported to use the EEPROM as switch to wire or reconfigure circuits in a FPGA design methodology. Altera and Xilinx offer field programmable chips to interconnect various CMOS hardware constructs to form complex circuit functions. The standalone FPGA devices support re-configurable control functions that are easy to change with instant deliverable parts.
Accordingly, what is needed is a system and method for providing a field programmable gate arrays (FPGA) which overcomes the above-identified problems. The present invention addresses such a need.